This disclosure relates to semiconductor devices and, in particular, semiconductor devices with isolation gates.
Standard cell logic gates made of semiconductor devices may be scaled to increase chip density. In addition, different cell layouts may be used to further increase chip density. However, adjacent transistors should be electrically isolated from one another. To isolate adjacent transistors, a break in a diffusion region may be used with a dummy gate region. Such a structure may require a separation of one or two times a contacted poly pitch of the semiconductor device. This distance limits the minimum spacing between transistors and hence, minimum cell size.